Methods for dicing a compound semiconductor wafer, and diced wafers and die obtained thereby

ABSTRACT

Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of application Ser. No.13/758,265, filed on Feb. 4, 2013, originally entitled “METHODS FORDICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINEDTHEREBY,” which has been allowed and which is hereby incorporated byreference herein in its entirety.

TECHNICAL FIELD OF THE INVENTION

The invention relates to semiconductor wafers and processes. Moreparticularly, the invention relates to methods for dicing a compoundsemiconductor wafer, and the diced wafers and die obtained by thosemethods.

BACKGROUND OF THE INVENTION

Semiconductor fabrication processes are multi-step processes that areused to create integrated circuits (ICs) that are used in a variety ofapplications. The process begins with the epitaxial growth of the waferfollowed by many processing steps, such as deposition processes (e.g.,chemical vapor deposition, molecular beam epitaxy, physical vapordeposition, atomic layer deposition), removal processes (e.g., wetetching, plasma etching, chemical-mechanical planarization), patterningprocesses (photolithography), and electrical property modificationprocesses (e.g., diffusion, ion implantation). Typically, hundreds ofsuch processing steps are performed to fabricate a wafer.

After the wafers have been fabricated, they are typically subjected to avariety of tests to verify that the wafers and the ICs formed on themmeet certain standards. After testing, the wafers are diced to divideeach wafer into many individual dies. Each die corresponds to an IC chipthat will later be packaged in an IC package that is ready for use.Different dicing techniques are used, such as scoring and breaking,sawing, laser cutting, and etching.

With respect to scribing and breaking or sawing, it is difficult toachieve side walls for the dies that are very smooth. Rather, the sidewalls of the dies are often rough or jagged, which can eventually leadto mechanical defects being formed in the dies (e.g., through chippingor cracking). For example, typical sawing or cutting techniques canresult in variations greater than 10 micrometers (microns) from die todie. In recent years, plasma etching tools and techniques have been usedto perform the dicing operations on wafers. Using plasma etching forthis purpose enables very precise dimensions for the dies to be obtainedand can result in the dies having very smooth side walls.

SUMMARY OF THE INVENTION

The invention provides a method for using a plasma etching process todice compound semiconductor wafers into dies, compound semiconductordies obtained thereby, and an array of passively-aligned compoundsemiconductor dies. The method comprises:

-   -   providing at least a first compound semiconductor die that has        been diced from a compound semiconductor wafer by a plasma etch        dicing process that provides the first die with at least one        side wall that has a known spatial relationship to at least one        element formed on or in a surface of the first CS die; and    -   passively aligning the first CS die with an external device by        placing the side wall in abutment with the external device. The        known spatial relationship of the side wall to the element        allows the side wall to be used as a passive alignment feature        such that passively aligning the side wall with the external        device results in passive alignment of the element of the die        with the external device.

The compound semiconductor die of the invention is a die that has beendiced by a plasma etch dicing process in such a way that a known spatialrelationship is created between at least one side wall of the die and atleast one element formed on or in a surface of the die. The knownspatial relationship of said at least one side wall to said at least oneelement allows said at least one side wall to be used as a passivealignment feature such that passively aligning said at least one sidewall with an external device results in passive alignment of said atleast one element with the external device.

The array of compound semiconductor dies comprises compoundsemiconductor dies that have been diced from one or more compoundsemiconductor wafers by a plasma etch dicing process that provides eachdie with at least one side wall that has a known spatial relationship toat least one element formed on or in a surface of the respective die.The known spatial relationships allow the respective side walls to beused as respective passive alignment features such that passivelyaligning the respective side walls of the respective dies with oneanother results in passive alignment of the respective elements of therespective dies with one another.

These and other features and advantages of the invention will becomeapparent from the following description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a pictorial diagram of the system in accordance withan illustrative embodiment, which is a plasma etching chamber that hasbeen adapted to perform plasma etching to dice compound semiconductorwafers into dies.

FIG. 2 is a flowchart that represents the method in accordance with anillustrative embodiment.

FIGS. 3A-3E are side plan views of a compound semiconductor wafer as itis processed in accordance with the method represented by the flowchartshown in FIG. 2.

FIGS. 4A-4F illustrate top plan views of compound semiconductor dieshaving a variety of shapes that have been made using the plasma etchingmethod and system described above with reference to FIGS. 1-3E.

FIG. 5 is a side perspective view of a plurality compound semiconductordies having a plurality of different shapes and sizes disposed on anadhesive-bearing surface of a piece of tape, which have been diced fromthe same wafer using the process described above with reference to FIGS.1-3E.

FIGS. 6A and 6B illustrate side views of a plurality of compoundsemiconductor dies disposed on an adhesive-bearing side of a piece oftape before and after, respectively, the piece of tape has beenstretched in the directions indicated by arrows.

FIG. 7A is a perspective view of a rectangular-shaped die obtained byusing the plasma etch dicing process described above with reference toFIGS. 1-3E.

FIG. 7B is a perspective view of an alignment base that has passivealignment features disposed on it for engaging with the die shown inFIG. 7A.

FIG. 7C is a perspective view of the alignment base shown in FIG. 7Bengaged with the die shown in FIG. 7A.

FIGS. 8A, 8B, 8C, and 8D are perspective views of a plurality of diesarranged in different side-by-side configurations, each of which isuseful in various applications.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

In accordance with the invention, methods are provided that use maskingtechniques and plasma etching techniques to dice a compoundsemiconductor wafer. Using these systems and methods allow compoundsemiconductor die to be obtained that have smooth side walls, a varietyof shapes and dimensions, and a variety of side wall profiles. Inaddition, by using these techniques to perform the dicing operations,the locations of features of the die relative to the side walls areascertainable with certainty such that one or more of the side walls canbe used as a passive alignment mechanism to precisely align features ofthe die with an external device. Illustrative embodiments of themethods, systems and the resulting dies will now be described withreference to the figures, in which like reference numerals representlike elements, components or features.

FIG. 1 illustrates a pictorial diagram of a plasma etching chamber thatmay be used to perform plasma etching to dice compound semiconductorwafers into dies. Plasma etching techniques have been used to dicecompound semiconductor wafers into dies, so any known techniques andtools are suitable for this purpose. The system 1 includes an etchingchamber 2, a cooling system 3, a first radio frequency (RF) power source4, and a second RF power source 5. In accordance with this illustrativeembodiment, the first RF power source 4 is a 13.56 megahertz (MHz) RFpower source and the second RF power source 5 is a 2 MHz RF powersource. The first RF power source 4 is used for setting the bias voltageof the semiconductor wafer 6, which is positioned on an adhesive-bearingside of a piece of tape 7. The piece of tape 7 is positioned on an uppersurface of a plate 8 that is electrically coupled to the first RF powersource 4. The second RF power source 5 is used for setting the biasvoltage of an upper plate 9, which is electrically coupled to the secondRF power source 5.

The first and second RF power sources 4 and 5 provide time-varyingelectrical currents that create time-varying magnetic fields about ararefied gas (not shown) disposed in the chamber 2. The time-varyingmagnetic fields induce electrical currents in the gas to create a plasma10. This process of creating plasma is referred to in the art as aninductively coupled plasma (ICP) process. The gas chemistry that is usedin the chamber 2 is typically based on either a methane base (CH₄) or achlorine base (Cl₂, BCl₃). Different gas ratios are used to etchdifferent types of compounds, and therefore the gas ratio that is usedto etch the wafer 6 will depend on the compound comprising the wafer 6.The wafer compound is typically a III-V compound (i.e., made up ofcombination of two or more of Ga, As, Al, In, and Ph).

FIG. 2 is a flowchart that represents the method performed by the systemshown in FIG. 1. FIGS. 3A-3E are side plan views of a compoundsemiconductor wafer 30 as it is processed in accordance with the methodrepresented by the flowchart shown in FIG. 2. The method will bedescribed with reference to FIGS. 2 and 3A-3E. Known photolithographicprocessing steps are performed to form openings, or channels, 31 (FIGS.3A and 3B) in a layer of photoresist 40 disposed on an upper surface ofthe wafer 30, leaving a patterned photoresist layer 40 a, 40 b and 40 con top of the upper surface of the wafer 30. This step is represented byblock 21 in FIG. 2 and the device shown in FIG. 3A. The patternedphotoresist layer 40 a-40 c acts as a mask that will protect the coveredportions of the wafer 30 from the subsequent plasma etching processwhile leaving the uncovered, exposed portions of the wafer 30 vulnerableto the subsequent plasma etching process. While photolithographicprocesses are well suited for creating the mask, any suitable processand material may be used to create the mask.

The wafer 30 having the patterned photoresist layer 40 a-40 c on it isthen placed on an adhesive-bearing side of a piece of tape 50, asindicated by block 22 in FIG. 2 and FIG. 3B. The tape 50 having thewafer 30 on it, as shown in FIG. 3B, is then placed inside of thechamber 2 shown in FIG. 1 and subjected to the plasma etching processdescribed above with reference to FIG. 1. This step is represented byblock 23 in FIG. 2 and by FIG. 3C. It can be seen in FIG. 3C that theportions of the wafer 30 that are not masked from the plasma etch by thepatterned photoresist layer 40 a-40 c are etched away, leaving only themasked portions of the wafer 30 and the photoresist 40 a-40 c disposedon top of it. The masked portions of the wafer 30 correspond to theindividual dies 30 a, 30 b and 30 c.

After the plasma etching process has been completed, the tape 50 havingthe wafer 30 thereon is removed from the chamber 2 and the remainingphotoresist layer 40 a-40 c is removed using ashing and chemical rinseprocesses (not shown for purposes of clarity), leaving only the tapehaving the dies 30 a, 30 b and 30 c thereon. This step is represented byblock 24 in FIG. 2 and by FIG. 3D. The tape 50 is then stretched in thedirections indicated by arrows 55 in FIG. 3E and by block 25 in FIG. 2to increase the lateral spacing between the dies 30 a-30 c. Stretchingthe tape 50 in this manner makes it easier for a pick-and-place machine(not shown for purposes of clarity) to be used to pick the dies 30 a-30c up off of the tape 50.

Using the plasma etching process described above to dice the wafer 30allows the dies to have any shape that can be defined by patterningphotoresist, unlike conventional techniques used for dicing compoundsemiconductor wafers, which only allow dies having fixed rectangularshapes to be formed. In addition, using the plasma etching processresults in the dies having very smooth side walls, which, as statedabove, is generally not the case with conventional sawing or cuttingsingulation processes used for dicing compound semiconductor wafers.With the plasma etch dicing process, smoothness of the side walls issuch that side wall variations from die to die are typically less than10 microns, and often less than 5 microns. Furthermore, using the plasmaetching process allows the dies to have any desired side wall profile.

In accordance with the invention, it has been determined that a plasmaetching process such as described above with reference to FIGS. 1-3E maybe used to dice wafers into dies that have non-rectangular shapes. FIGS.4A-4F illustrate top plan views of compound semiconductor dies having avariety of non-rectangular shapes that have been made using the plasmaetching method and system described above with reference to FIGS. 1-3E.The die shapes shown in FIGS. 4A-4E are a torus 110, a cross 120, apentagon 130, a triangle 140, and a parallelogram 150, respectively. Thedie shape 160 shown in FIG. 4F is an irregular, non-rectangular shapehaving a variety of angles, side wall dimensions and side wall profiles.With conventional sawing or cutting dicing processes often used fordicing compound semiconductor wafers, the indexing of the sawing orcutting tool is fixed, so the die size and the channel width (i.e., thedistance between dies) is fixed. Also, with conventional sawing orcutting dicing processes, the sawing or cutting tool is limited tomaking cuts that are orthogonal to one another such that the dies alwaysare rectangular in shape.

With the plasma etch dicing process, a variety of nonrectangular dieshapes are obtainable, such as those shown in FIGS. 4A-4E, for example.Essentially, any pattern that can be photolithographically formed in thephotoresist layer can be transferred onto the wafer to define the shapeof the dies. One of the advantages of being able to dice compoundsemiconductor wafers into dies having non-rectangular shapes is that itallows the shape of the resulting die to be used as a passive alignmentfeature for precisely aligning the die with an external device orelement. Being able to use the shape of the die as a passive alignmentfeature allows a feature located on one of the surfaces of the die to bebrought into alignment with an external device or element by passivelyaligning one or more walls of the die with an external device or featurehaving a shape that is complementary to the shape of the die wall orwalls that are being used as the passive alignment feature. For example,this passive alignment method could be used to bring a light-emittingfacet of a laser diode die into optical alignment with a lens or an endof an optical fiber. As another example, this passive alignment methodcould be used to bring a light-receiving facet of a photodiode die intooptical alignment with a lens or an end of an optical fiber.

FIG. 5 is a side perspective view of a plurality dies having a pluralityof different shapes and sizes disposed on an adhesive-bearing surface ofa piece of tape 200, which have been diced from the same wafer using theprocess described above with reference to FIGS. 1-3E, except that theprocess has been adapted in accordance with embodiments of the inventionto achieve the different die shapes and sizes. The shapes of these dies210, 220, 230, and 240 are obtained by carefully controlling thepatterned photoresist layer (not shown for purposes of clarity) and/orits thickness. For example, with respect to die 210, this shape could beachieved by, for example, making the patterned photoresist layer thinnertoward the outer edges of the intended die 210 and thicker elsewhere,causing the wafer to etch faster along the outer edges than in otherareas in order to make the side walls curved. With respect to die 220,the patterned photoresist layer would have had a uniform thickness. Withrespect to die 230, the patterned photoresist layer would have beenthinner toward the outer edges of the intended die 230 and thickerelsewhere, causing the wafer to etch faster along the outer edges thanin other areas. The same would be true for die 240.

In addition, the plasma etching need not be directional (i.e., straightdown in a direction normal to the tape 200) in all cases. The gaschemistry may be changed during the etching process. Because differentsemiconductor compounds etch at different rates for different gaschemistries, using more than one gas chemistry during the etchingprocess can result in different die shapes, such as the arched uppersurfaces of the dies 230 and 240 and the curved side walls of die 210.

FIGS. 6A and 6B illustrate side views of a plurality of compoundsemiconductor dies 260-330 disposed on an adhesive-bearing side of apiece of tape 250 before and after, respectively, the piece of tape 250has been stretched in the directions indicated by arrows 255. The dies260-330 do not all have the same width-wise dimensions. For example,dies 310 and 320 have widths W1 and W2, which are not the same. Also thechannel spacing 350 between the dies 310-330 is not exactly the same forall of the adjacent dies 310-330 on the piece of tape 250. Thewidth-wise dimensions of the dies 310-330 and the channel spacingbetween the dies 310-330 is easily controllable by controlling thepatterning of the photoresist layer (not shown for purposes of clarity)described above with reference to FIGS. 1-3E. The manner in which thephotoresist layer may be patterned is well known, and therefore will notbe described herein. The manner in which plasma etching is performed isalso well known, and therefore will not be described herein.

As indicated above, using plasma etching to dice the dies results in thedies having very smooth side walls compared to the relatively rough orjagged side walls of the dies that often result from dicing processesthat use cutting or sawing. In accordance with embodiments of theinvention, it has been determined that this characteristic ofplasma-etched dies can be used to make a physical feature of the die,such as a side wall, for example, a passive alignment feature. FIG. 7Ais a perspective view of a rectangular-shaped die 360 obtained by usingthe plasma etch dicing process described above with reference to FIGS.1-3E. One of the advantages of this feature is that it allows the sidewalls of the dies to be used for passive alignment purposes to achievevery precise passive alignment of the die with some other object, deviceor element. This has generally not been possible when using sawing orcutting to dice compound semiconductor wafers due to the possibility ofthe side walls being too rough. An example of the manner in which thesmooth side walls of the die 360 make it suitable for use in a passivealignment scenario will now be described with reference to FIGS. 7A-7C.

FIG. 7B is a perspective view of an alignment base 370 that has passivealignment features 370 a and 370 b disposed on it. For this example, itis assumed that the base 370 is very precisely formed in terms of itsdimensions and locations of features 371 and 372. The features 371 and372 are precisely dimensioned and spaced apart to match the width, W,and height, H, dimensions of the die 360 (FIG. 7A). Each of the features371 and 372 has a pair of side walls 371 a′ and 371 a″ and 372 a′ and372 a″, respectively, that forms a right angle that precisely matchesthe right angles formed by the bottom and left side surfaces 360 a, 360b and the bottom and right side surfaces 360 a, 360 c of the die 360.Therefore, when the die 360 is precisely aligned with the features 371and 372, the die fits precisely in the rectangular space defined by thepairs of side walls 371 a′ and 371 a″ and 372 a′ and 372 a″.

FIG. 7C is a perspective view of the alignment base 370 engaged with thedie 360. Because of the smoothness of the side walls 360 a-360 c of thedie 360, it can be ensured that when the die 360 is engaged with thealignment base 370, the die 360 is in precise alignment with the base370. This, in turn, ensures that any feature disposed on or formed inthe side wall 360 c of the die 360 is at a very precise locationrelative to the base 370. Thus, placing the base 370 at aprecisely-defined location relative to some other device or structure(not shown for purposes of clarity), ensures that the die 360 is at aprecisely-defined location relative to that same device or structure.This is very beneficial, especially in cases where the die is a laserdiode or a photodiode having a light-emitting or light-receivingaperture, respectively, that needs to be precisely optically alignedwith another element, such as a lens, for example. For example, if thedie is a laser diode and the feature 365 is a light-emitting aperture ofthe laser diode, precise optical alignment of the base 370 with anexternal optics system (not shown for clarity) would result in preciseoptical alignment of the light-emitting aperture 365 with the externaloptics system.

FIGS. 8A, 8B, 8C, and 8D are perspective views of a plurality of dies400 arranged in different side-by-side configurations, each of which isuseful in various applications. For exemplary purposes, it will beassumed that the dies are laser diodes, such as vertical cavity surfaceemitting laser diodes (VCSELs). One of the difficulties associated withmanufacturing semiconductor dies that have arrays of laser diodes isthat if any of the laser diodes on the die is defective, the die isdiscarded. This reduces yield and increases costs.

One way to avoid the risk of having to discard a die that containsmultiple laser diodes due to one of the laser diodes being defective isto singulate the wafer into individual dies and then mount dies that areknown to be non-defective in a side-by-side arrangement to form arraysof a desired size. Because the side walls of the dies can be made verysmooth by using the plasma etch dicing process described above, the diescan be used as singlets 400 (FIG. 8A) that are mounted separately usingan alignment base such as that shown in FIGS. 7B and 7C, they can beplaced in abutment with one another to form a subarray 410 (FIG. 8B), ormultiple subarrays 410 can be placed in abutment with one another toform a larger array 420. The smooth side walls of the dies 400 allowsthe side walls to be used to passively align the dies 400 with adjacentdies 400 in the subarray 410 or the larger array 420. The same is trueif the dies 400 were some other type of die, such as photodiode dies,for example. The ability to create arrays of laser diodes or photodiodesin this manner with precise alignment is very useful in paralleltransmitters, receivers and transceivers.

It should be noted that the invention has been described with respect toillustrative embodiments for the purpose of describing the principlesand concepts of the invention. The invention is not limited to theseembodiments. For example, while the invention has been described withreference to obtaining certain die shapes, the invention is not limitedto the die shapes described herein or shown in the figures. Persons ofskill in the art will understand, in view of the description beingprovided herein, that the processes described above can be varied toachieve a variety of other die shapes. Those skilled in the art willunderstand, in view of the description being provided herein, that manymodifications may be made to the embodiments described herein whilestill achieving the goals of the invention and that all suchmodifications are within the scope of the invention.

What is claimed is:
 1. A compound semiconductor die diced from acompound semiconductor wafer by a plasma etch dicing process in such away that a known spatial relationship is created between at least oneside wall of the die and at least one optical element formed on or in asurface of the die, and wherein the known spatial relationship betweensaid at least one side wall and said at least one element allows said atleast one side wall to be used as a passive alignment feature such thataligning said at least one side wall with a first alignment featureextending upwardly from a top surface of an external device results inalignment of said at least one optical element with the external device.2. The compound semiconductor die of claim 1, wherein the die has ashape of a rectangle.
 3. The compound semiconductor die of claim 1,wherein: the plasma etch dicing process that is used to dice the waferprovides the die with at least first and second side walls that haveknown spatial relationships to said at least one optical element and toone another, and the known spatial relationships allow the first andsecond side walls to be used as passive alignment features such thataligning the first side wall with the first alignment feature of theexternal device and aligning the second side wall with a secondalignment feature extending upwardly from the top surface of theexternal device results in alignment of the external device with said atleast one optical element.
 4. The compound semiconductor die of claim 3,wherein the external device is an alignment base, and wherein the firstand second alignment features each further include a first sidewall andsecond sidewall forming a right angle and the first alignment featureand second alignment feature are positioned on the top surface of thealignment base so as to receive the first die.
 5. The compoundsemiconductor die of claim 4, wherein the alignment base is configuredto be aligned with a second external structure such that the alignmentof said at least one optical element with the alignment base results inalignment of said at least one optical element with the second externalstructure.
 6. The compound semiconductor die of claim 3, wherein thefirst and second side walls are substantially perpendicular to oneanother, and wherein said at least one optical element is formed on orin a surface of the die that is substantially perpendicular to the firstand second side walls.
 7. The compound semiconductor die of claim 3,wherein the die has a shape of a rectangle, and wherein the first andsecond side walls are substantially parallel to one another andsubstantially perpendicular to said surface.
 8. The compoundsemiconductor die of claim 1, wherein the die has a non-rectangularshape.
 9. The compound semiconductor die of claim 1, wherein the die isa laser diode die and wherein said at least one optical element is alight-emitting facet of the die.
 10. The compound semiconductor die ofclaim 1, wherein the die is a photodiode die and wherein said at leastone optical element is a light-receiving facet of the die.
 11. Thecompound semiconductor die of claim 1, wherein the external device is analignment base and the first alignment feature further includes a firstsidewall and a second sidewall forming a right angle configured toreceive the die.
 12. An array of compound semiconductor (CS) dies,wherein the CS dies have been diced from one or more CS wafers by aplasma etch dicing process that provides each CS die with at least oneside wall that has a known spatial relationship to at least one opticalelement formed on or in a surface of the respective CS die, and whereinthe known spatial relationships allow the respective side walls to beused as respective alignment features such that aligning the respectiveside walls of the respective CS dies with one another results inalignment of the respective optical elements of the respective CS dieswith one another.
 13. The array of claim 12, wherein at least two of theCS dies of the array have different dimensions.
 14. The array of claim12, wherein at least two of the CS dies of the array have differentshapes.
 15. The array of claim 12, wherein at least two of the CS dieshave different functions.
 16. The array of claim 12, wherein at leasttwo of the CS dies are laser diode dies having different operatingwavelengths.
 17. The array of claim 12, wherein at least two of the CSdies are photodiode dies having different operating wavelengths.
 18. Thearray of claim 12, wherein at least one of the CS dies is laser diodedie and at least one of the CS dies is a photodiode, and wherein saidoptical element of the laser diode is a light-emitting facet and whereinsaid optical element of the photodiode is a light-receiving facet. 19.The array of claim 12, wherein at least two of the CS dies have beendiced from different CS wafers and are made of different materials. 20.The array of claim 12, wherein at least two of the CS dies have beendiced from a same CS wafer and are made of a same material.